1. Technical Field
The disclosure relates in general to a three dimensional stacked multi-chip structure and manufacturing method of the same, and more particularly to a three dimensional stacked multi-chip structure including chip-enable areas having different conductive states and manufacturing method of the same
2. Description of the Related Art
A manufacturing method of a three-dimensional integrated circuit (3D IC) is stacking and bonding a number of semiconductor wafers vertically to create an individual three-dimensional integrated circuit. Generally, the edges of adjacent chips can be staggered in a stair step and a wire bonding method is used to connect the pads on the chips. Besides, another method for making electrical connections between stacked chips, which called a through-silicon via (TSV) process, may be used. Comparing to the conventional wire bonding method, using the through-silicon via process can exhibit a wider bandwidth and shorter connection path which enhances speed and lowers power consumption.
However, the through-silicon via process requires a plurality of steps for each wafer, such as photoresist deposition, etching, silicon dioxide deposition, barrier seed deposition, photoresist patterning, photoresist removal, chemical mechanical polishing, and support/handling die bonding, etc. In addition to the time and expense required for all the steps, the required handling and processing of each die results in lower yields. Moreover, it is quite challenge to handle thin wafers during the process discuss above.